HV Interlock Loop — symbol and terminals
The HV Interlock Loop is an educational high-voltage model used in the EV High Voltage section of the lab. Safety interlock loop through HV connectors. Place the symbol on the schematic, wire the listed terminals and run the solver to explore its behaviour. Models are simplified for teaching and must not be used to design or service real equipment.
| Terminal | Name | Function |
|---|---|---|
| in | Interlock In | left |
| out | Interlock Out | right |
Standard reference: IEC 60617 / IEC 61851. Symbols are original educational drawings; always verify against the applicable standard and manufacturer documentation.